This project aims to explore the use of two-dimensional transition metal dichalcogenides (TMDs), such as MoS2 and WSe2, as neuromorphic devices. We will leverage the extremely low leakage current of wide-bandgap TMD materials to develop floating-gate transistors (FGFETs), where changes in charge stored at the floating gate alter the MoS2 channel conductance. Floating gate structures will be first simulated and then experimentally demonstrated on TMD’s grown by metal-organic chemical vapor deposition (MOCVD) at back-end-of-line (BEOL)-compatible temperatures and integrated on a standard silicon CMOS process. For this, we will build on the MoS2 low-temperature 200 mm wafer-scale MOCVD growth technology recently demonstrated by our group, and we will fabricate highly-scaled heterostructure-based devices to ensure reproducible neuromorphic devices with record-low power consumption. We will also explore the impact of different processing steps such as lithography and deposition conditions on the device performance and stability.

In collaboration with Jing Kong, Jerry Mcafee (1940) Professor In Engineering, Electrical Engineering and Computer Science

This research presents a general method for secure machine learning hardware using a digital in-memory compute architecture through decorrelation of circuit currents from neural network data, encrypting off-chip model storage, and local secret key generation.

In collaboration with Anantha Chandrakasan, Chief Innovation and Strategy Officer; Dean, MIT School of Engineering; Vannevar Bush Professor of Electrical Engineering and Computer Science

The role of Large Language Models (LLMs) has not been extensively explored in analog circuit design, which could benefit from a reasoning-based approach that transcends traditional optimization techniques. In particular, despite their growing relevance, there are no benchmarks to assess LLMs’ reasoning capability about circuits. Therefore, we created the CIRCUIT dataset consisting of 510 question-answer pairs spanning various levels of analog-circuit-related subjects. The best-performing model on our dataset, GPT-4o, achieves 48.04% accuracy when evaluated on the final numerical answer. To evaluate the robustness of LLMs on our dataset, we introduced a unique feature that enables unit-test-like evaluation by grouping questions into unit tests. In this case, GPT-4o can only pass 27.45% of the unit tests, highlighting that the most advanced LLMs still struggle with understanding circuits, which requires multi-level reasoning, particularly when involving circuit topologies. This circuit-specific benchmark highlights LLMs’ limitations, offering valuable insights for advancing their application in analog integrated circuit design.

In collaboration with Ruonan Han, Associate Professor, Electrical Engineering and Computer Science

We aim to create models for new fault modes in processors, addressing reliability challenges for large-scale data centers. Our research develops methods for designing resilient hardware, guiding cost-effective protection strategies for scalability.

In collaboration with Mengjia Yan, Assistant Professor, Electrical Engineering and Computer Science, and Joel S. Emer, Professor of the Practice, Electrical Engineering and Computer Science

The rapid advancement of generative AI, particularly large language models (LLMs), presents unprecedented computational challenges. LLMs boast billions of parameters (e.g., Llama3: 70B),more than 1000× larger than TinyML models. The autoregressive nature of LLMs makes inference memory bounded. Generating long sequences further compounds the memory demand. Our research addresses these challenges by quantization, low-precision systems and KV cache optimization.

In collaboration with Song Han, Associate Professor, Electrical Engineering and Computer Science

This talk will explore calibration and optimality in programmable photonics, with a focus on error robustness and efficient phase-shifter usage in multiport interferometers. We examine the challenges in designing photonic circuits that are both efficient and robust to errors, particularly in the context of optical neural networks, boson sampling, and other advanced applications. Highlighting mesh architectures such as the Reck and Clements designs, the talk addresses how phase requirements can be minimized while maintaining system universality and low error sensitivity. We propose a novel 3-MZI structure, which reduces phase-shift demands and improves fault tolerance by offering more stable configurations. This architecture, when evaluated against information-theoretic bounds, approaches optimal phase efficiency for large-scale photonic meshes. Applications in self-configuring systems, error-aware training, and non-unitary photonic meshes will also be discussed, presenting a comprehensive approach to achieving near-optimal programmable photonic performance.

In collaboration with Dirk Englund, Associate Professor, Electrical Engineering and Computer Science

CMOS (Complementary Metal-Oxide-Semiconductor) technology and fabrication processes, the backbone of many in integrated circuits, provides several advantages: low power consumption, high density, scalability, and cost-effectiveness. Researchers are combining this with proton-based synapse elements that resemble human brain structures, making them well-suited for AI applications. This research focuses on integration using tungsten oxide, phosphosilicate glass (PSG) and a solid electrolyte in the fabrication process of different size arrays.

In collaboration with Jesús del Alamo, Donner Professor and Professor of Electrical Engineering, Department of Electrical Engineering and Computer Science