Most advanced AI ICs components will require downscaled technologies beyond 2 nm and massive heterogeneous integration on package level to satisfy the power-performance need of future AI applications. They will be applied in safety critical and rough environments like for autonomous vehicles where high reliability standards need to be fulfilled for the system. On the level of the IC design minute dimensions and complex integration schemes of Die-to-Die interfaces in the Millions will make the IC more and more susceptible to thermo-mechanical and electrical stress conditions. A careful co-design of system measures and IC design have to be applied based on the deep understanding of the physical phenomena and the proper characterization and modelling of the IC components. The talk will sketch out the technology trends and the resulting challenges for robustness design. Two examples of electrical stress (ESD) and thermo-mechanical (warpage) will highlight the current effort of industry to comply with these needs.
This event is part of the NanoBio Seminar Series.

Speaker
Harald Gossner
Harald Gossner is Senior Principal Engineer at Intel. He received his diploma degree in physics from Ludwig-Maximilians-University, Munich in 1990 and his PhD in electrical engineering from Universität der Bundeswehr, Munich in 1995. For 15 years he has worked on the development of ESD protection concepts with Siemens and Infineon Technologies. In 2011 he joined Intel leading the system ESD robustness development for Intel products. Harald Gossner has authored and co-authored 150 technical papers and two books in the fields of IC robustness design and device physics, where he also holds 120 patents. He is the recipient of the outstanding achievement award of EOS/ESD Association as highest award for his contributions to the field of ESD. He is the cofounder and co-chair of the Industry Council on ESD Target Levels. He also served as president of the EOS/ESD Association, Rome, NY, from January 2022 to December 2023. Harald Gossner is IEEE Fellow and contributes as editor to IEEE EDL. Currently he is member of the industry advisory boards of the Bavarian Government and Fraunhofer institutes and participates in the expert commission on AI of the German Economic Council. He is project lead of the project Semiconductor-X, coordinating the development of a resilient supply chain of semiconductors for Europe.
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