CMOS-Compatible Ferroelectric Synapse Technology for Analog Neural Networks

Principal Investigator: Jesús del Alamo

The recent discovery of prominent ferroelectric properties of CMOS-compatible HfO₂-based materials has brought new functionality to Si microelectronics in the form of a new memory technology and the potential of transistors that can operate at very low voltages. An intriguing new application of these remarkable findings is in low-energy analog synapses. The demonstration of partial ferroelectric switching following very short (sub-µs) and low-voltage (sub-1 V) pulses suggests the viability of this concept. A relevant synapse technology has to leverage the CMOS infrastructure and so it must be immersed among the interconnect layers at the top of a CMOS chip (“the back end”). This enables the design of analog AI chips that combine ferroelectric analog arrays with analog/digital interface circuits and standard digital memory. This research project investigates a new ferroelectric synapse technology based on metal oxides that is designed to be fully back-end CMOS compatible.